The present embodiments relate to semiconductor devices and methods and are more particularly directed to a stacked decoupling capacitor structure.
Semiconductor devices are prevalent in countless different aspects of contemporary society, and as a result, the marketplace for such devices continues to advance at a fairly rapid pace. This advancement is evident in many respects and relates to semiconductor devices either directly or indirectly as well as the methods for forming such devices. For example, the advancement affects numerous device attributes and increases the need for attention to such attributes during design and manufacturing, where such attributes include device size, reliability, yield, and cost. These aspects as well as others are addressed by the prior art and are further improved upon by the preferred embodiments as detailed below.
By way of further background, the preferred embodiments relate to decoupling capacitors formed integrally with an integrated circuit. Decoupling capacitors are used to “decouple” or isolate a signal on a conductor. A common example is connecting a decoupling capacitor between a supply voltage and ground such that any transient or other noise signal affecting the power supply is suppressed by the capacitor, thereby decoupling that signal from other components in the device. While formerly decoupling capacitors were sometimes implemented using separate discrete devices, with the continued advancement of integrated circuits a polysilicon to N-well decoupling capacitor also has been developed. As a capacitor in general, this device includes two conductive plates separated by a dielectric. More specifically and as suggested by its name as a polysilicon to N-well decoupling capacitor, one layer of doped polysilicon forms one of the capacitor's conductive plates while an N-well, formed within either another well or within a semiconductor substrate, forms the other conductive plate. Lastly, these two plates are separated by a dielectric, which is typically silicon dioxide formed at the same time and from the same material that is also used to form the gate dielectric for various transistors being formed with respect to the same well or substrate.
While polysilicon to N-well decoupling capacitors have been used successfully in various devices, various drawbacks have been observed in such devices as performance demands increase. Particularly, with increased performance demands, there is a corresponding increase in the need for total decoupling capacitance. Further, the location of decoupling capacitors may be distributed in numerous locations across an integrated circuit die. Thus, when using polysilicon to N-well decoupling capacitors in an attempt to satisfy demands, there is a trade-off in that larger amounts of chip area are required to implement the capacitors, where it is well-known that such area can be quite costly in terms of design and, indeed, in some instances, prohibitive. As another consideration, recall that present polysilicon to N-well decoupling capacitors use the transistor gate dielectric layer as a dielectric between the capacitor plates. However, there also is a trend in the transistor art to decease the thickness of these gate dielectrics, which correspondingly decreases the amount of capacitive material in the polysilicon to N-well decoupling capacitors. Such a result is undesirable for the capacitor for two reasons. First, it increases the chance of capacitor leakage because the likelihood of leakage increases as dielectric thickness decreases and the need for decoupling increases. Second, with a thinner capacitive dielectric, there is a greater chance of an electrical short-circuit through the dielectric and, hence, between the capacitor plates. The N-well in such a case may provide some resistance to the current flowing through the short-circuit so as to prevent a total device failure, yet the decoupling effect is lost and, hence, with a sufficient number of such failures then device yield is reduced and/or circuit performance is reduced.
In view of the above, the present inventors provide below alternative embodiments for improving upon various drawbacks of the prior art.